1. Field of the Invention
The present invention relates to a circuit design system and a circuit design system program used in designing a logic circuit. In particular, the present invention relates to a circuit design system and a circuit design system program used for facilitating a failure analysis.
2. Description of the Related Art
In an ordinary process of manufacturing semiconductor integrated circuits, defective products are included in the manufactured semiconductor integrated circuits to some degree. The defective products are eliminated in a test process and only non-defective products are shipped. Here, a rate of the non-defective products at this time is referred to as “yield”. If the yield is low, then cost of manufacturing goods is increased and profit is declined. It is therefore necessary to establish a cause of the defect by a failure analysis and to enhance the yield by improving the manufacturing process.
However, the failure analysis is becoming more and more difficult as the integration degree of the semiconductor integrated circuit becomes higher. For example, it is difficult to make a potential waveform measurement (electron beam (EB) measurement) by using an electron beam apparatus, because the number of interconnection layers increases up to about eight in the present state and a measurement-target interconnection is not exposed in many cases. Alternatively, an LVP (Laser Voltage Probe) measurement may be used. The LVP measurement is a method of measuring a potential waveform by applying a laser beam onto a rear surface of a chip, and is available even if the number of interconnection layers is large (refer to, for example, National Publication of Translated Version JP-P2002-522770 and corresponding U.S. Pat. No. 6,072,179). However, in and after the generation of 90 nm, not all the transistors can become the measurement target due to lack of resolution.
Moreover, the following method is also known as a method of measuring a potential waveform in an integrated circuit. That is, the EB measurement is made after interconnections are exposed by using a focused ion beam (FIB) apparatus. However, the method requires an awful lot of operating time. For this reason, it is necessary to estimate a fault position roughly by using fault diagnosis software in advance and to specify the fault position through the measurement on the basis of the estimation result. Here, the fault diagnosis software is software that “estimates” the fault position based on a circuit diagram of a design-target integrated circuit and a test result. Moreover, the fault position extracted by the estimation is called a “fault candidate”.
In this case, the number of fault candidates estimated by the above-mentioned fault diagnosis software can become very large, depending on the structure of the design-target integrated circuit. If so, it is necessary to make a measurement to confirm which fault candidate is a real fault. In the measurement, interconnections are exposed by the FIB apparatus, as already stated. Therefore, as the number of fault candidates becomes larger, the measurement time becomes longer, resulting in an increase in an operation time required for the failure analysis.
Meanwhile, a logic design program for facilitating the failure analysis is disclosed in Japanese Laid-Open Patent Application JP-P2001-14370. According to the technique disclosed in the patent document, a design of an integrated circuit is changed so that a designated observation-target interconnection can be observed by a failure analysis means (e.g., the EB measurement or the LVP measurement). A specific configuration of a circuit design system according to the conventional technique is shown in FIG. 1, and its operation is described with reference to FIG. 1.
First, circuit connection information (netlist) is input to a placing and routing means 2003 through an input means 2001. Referring to the circuit connection information, the placing and routing means 2003 performs cell placement and interconnection routing. Next, a judgment means 2005 receives an observation-target designation data through the input means 2001, and judges whether or not a circuit region designated by the observation-target designation data is observable by a failure analysis means. In a case where the circuit region is not observable, a replacement indicating means 2007 generates an interconnection-replacement order data for making the circuit region observable. The placing and routing means 2003 generates a new layout data based on the interconnection-replacement order data. That is, the placing and routing means 2003 changes the circuit layout such that the circuit region becomes observable by the predetermined failure analysis means. The new layout data is input to a circuit manufacturing apparatus 2009. As a consequence, an integrated circuit in which the failure analysis is facilitated is manufactured.
Furthermore, the patent document (Japanese Laid-Open Patent Application JP-P2001-14370) describes that an observation point is inserted into a fault undetected region or a circuit region with poor controllability and observability in the integrated circuit. However, a specific method of deciding an insertion position into which the observation point is inserted is not described in the patent document. Moreover, if the observation point is inserted into each of all circuit regions with poor observability, the area of the circuit and the overhead of operating speed become considerable and unignorable, which is a problem.
Meanwhile, a method of selecting observation points for improving failure-analyticity with fewer observation points is described in Irith Pomeranz, Srikanth Venkataraman, and Sudhakar M. Reddy, “Z-DFD: Design-for-Diagnosability based on the concept of z-detection”, Proceedings of International Test Conference 2004, November 2004 (referred to as a “Non-patent Document” throughout the present specification). According to the method, observation points are first inserted into all nodes within a circuit by referring to a gate-level circuit connection information (netlist). Next, the number Np of faults (equivalent faults) whose positions can not be specified by an external measurement is calculated. At this time, the number Np is equal to zero, because all the nodes within the circuit are observable. Thereafter, an observation point is eliminated from such a node as from which the number Np does not increase even if the observation point is eliminated or such a node as from which an increase in the number Np is small even if the observation point is eliminated. The elimination is repeated. As a result, some observation points are eliminated while the increase in the number Np is suppressed as possible. It is thus expected that the failure-analyticity is improved with a small number of observation points.
As a technique related to the circuit design, a “physical synthesis method” is known. The physical synthesis method is described, for example, in Toshihiro Terazawa, Tatsuya Higashi, Yoshinori Watanabe, Takayoshi Shimazawa, Masafumi Takahashi, and Tohru Furuyama, “The Importance of Physical Synthesis for the advanced LSI process technology”, Technical Report of the Institute of Electronics, Information and Communication Engineers (IEICE), VLD2000-138, ICD2000-214, from p. 25, March 2001. Also, the physical synthesis method is described in “Reuse Methodology Manual for System-on-a-Chip Designs”, ISBN:1402071418, by Michael Keating and Pierre Bricaud, SPRINGER NETHERLANDS. FIG. 2 is a flowchart showing the physical synthesis method. First, functions of a desired circuit are designed (Step S2101). Next, logic synthesis and cell placement are carried out simultaneously in parallel (Step S2103). It should be noted here that logic synthesis of the entire circuit is not performed all at once but that logic synthesis of one to a few cells is performed and then placement of the cells is immediately performed. Thereafter, clock tree synthesis and routing are carried out (Step S2105). Then, a delay time of a signal is calculated from a distance between cells, and the logic and the cell placement are optimized (Step S2107). By repeating the above-mentioned procedures, the entire circuit is designed.